Binary adder and subtractor
A full binary adder must satisfy the follow ng truth table:. The fourth column shows the sum output T for each of these eight combinations, and the fifth column shows the carry out G output for each of these eight combinations.
Conversely, when it is desired to subtract one binary number from another, i. A full binary subtracter is a device which will subtract 2. A full binary subtracter must satisfy the following truth table:. The fourth column shows the difference T output for each of these eight combinations, and the fifth column shows the borrow out G output for each of these eight combinations.
In addition to the add and subtract functions, an arithmetic unit, to be truly useful, must also be capable of modifying or adjusting these add or subtract functions in accordance with the needs encountered in the more complex arithmetic operations of multiply, divide, root taking, power generation, etc. Such operations impose on the arithmetic unit the additional requirement that it must be capable of functioning in such a manner as to bypass or ignore a subtrahend or addend with respect to the difference or sum outputs, respectively, and yet continuously provide a signal indicating a borrow or carry just as if the subtrahend or addend were to be used in the particular operation.
This bypass function, briefly explained here, is more fully explained in copending application Ser. We shall refer below to this bypass control or function as the K control or function. To accomplish these bypass functions, the arithmetic unit must satisfy the additional truth tables following:. These truth tables reflect the actual results obtained from the arithmetic units described below as preferred embodiments.
It is recognized that line 7 of Table No. However, the simplicity of the preferred embodiments is advantageous for the sub-' tract function which is of primary importance when the improved arithmetic unit is used in a matrix for performing division and root taking. The K factor is rarely required for addition, but the preferred circuits can be redesigned to correct the above inaccuracy if so desired.
The P after Diff indicates a permitted trial substraction or positive difference and an NP indicates a not permitted trial substraction or negative difference. This prior art technique, while accurate, is inefficient with respect to time, operations, and hardware. The extra steps resuired to add a compensating value when a not permitted subtraction is attempted significantly slows down the division process, since the additional steps of addition are not pertinent to the problem and represent inefficient machine usage.
Furthermore, in those cases where the division is done in a matrix, the inclusion of matrix elements to handle the corrective additions doubles the size of the required matrix. Moreover, if the matrix size is reduced, then the corrective addition must be performed by bistable elements which isolate the remaining calculations from the initial divisor and dividend. The result is that, if a change occurs in the divisor or the dividend, then complex, usually expensive, circuitry must be used to detect the change, halt the process and recycle, thereby increasing the effective response time of the unit.
These foregoing difiiculties while bad enough with respect to division, are much more serious in the problems involving root takmg. In the copending application referenced above, inventions that correct this difficulty are described. As a result r 4 of these inventions, the same division would be performed as follows:. The indicates a sensed unsatisfied borrow representing a negative difference which generates a K control signal which in turn causes the associated trial subtrahend to be bypassed and the minuend for that matrix level to be repeated on the output terminals for that level so as to be able to serve as the minuend for the next lower level trial substraction.
The advantages of a computer operating with K control are fully discussed in the copending application, and include: The fourth advantage is very important in that it permits the computer to operate must closer to real time than is possible with prior art digital arithmetic complexes. In other words, this invention provides direct and continuous control of the matrix elements by the digital input number signals, thereby permitting calculations to be performed as close to real time as allowed by the time response characteristics of the components employed.
Even though the improved arithmetic unit is described herein as a part of full parallel or matrix arithmetic complexes, it is to be understood that the same advantages result when the arithmetic unit is used in serial or block serial arithmetic complexes. Many prior art full binary adders and subtracters are known. However, none is known which has the capability of bypassing a function, while at the same time maintaining circuit awareness of the effect of not bypassing the function.
Such a capability is particularly required in the high speed utilization of parallel computation techniques generally and, in certain aspects, serial computation techniques. This capability is especially important when the arithmetic unit is combined in an arithmetic complex see the above copending application which is to perform multiplication, division, power generation and root taking without non-pertinent peripheral computations.
In addition, prior art full binary adders and subtracters usually have certain disadvantages in that 1 they rely on so-called standard logic symbols for their formation and explanation, and 2 they are constructed unilaterally in terms of either increased signal logic or decreased signal logic. The first restriction is detrimental in that it does not easily show where elements of an AND gate may, for example, combine with, or perform duties in, an OR gate in order to perform some such function as inhibit or.
The second restriction generally results in the inclusion of devices, such as inverters, to convert signals, that have been changed from plus logic to minus logic by the mathematics, back to plus logic. Both restrictions result in undue circuit complexity and the incorporation of unnecessary active or passive elements with attendant increase in circuit delay, instability and unreliability.
For example, an important feature of this invention is the provision of an improved adder-subtracter having means for bypassing a function, such as addend or sub tracting a subtrahend, but at the same time providing a signal representing a carry or borrow which would have been generated if the function had not been bypassed. In the prior art, there is a diversity of methods for representing the signal state of the various points of a logical block diagram, such as: This problem of choosing appropriate symbols is further complicated by the Well-known capability of most computing devices to work interchangeably in two different modes depending on the input signals; thus, a conventional diode-resistor OR gate for circuits where a high voltage represents a logical 1 and a low voltage represents a logical zero, will function as an AND gate in those circuits where a high voltage represents a logical zero and a low voltage represents a logi cal one.
Since this invention uses both logic conditions, it becomes expeditious to define the signal states only in terms of whether or not a signal exists. This will create no hardship for those skilled in the art and will provide a much simplified explanation. For those less skilled, the explanation, below, of the operation of the preferred embodiment of FIG.
Accordingly, a zero is considered to exist at any point in a logic device when that point is at its at rest or null state as determined by the condition that all input signals to the device are zero.
Conversely, a one is said to exist when the point is significantly disturbed from its null position or state. In the same sense the two conditions will be designated as N for null or no signal, i.
Summary of the invention Therefore, the primary object of the invention is to provide an improved arithmetic unit having a function bypass control. Another object is to provide an improved full binary adder-subtracter having means to bypass a function and also means to generate a signal representing the effect of the bypassed function just as if it had not been bypassed.
A further object is to provide an improved binary arithmetic unit which can be controlled to perform either addition or subtraction.
Still another object is to provide an improved logic circuit incorporating suppression logic to provide function bypass control in addition and subtraction operations. A further object is to provide an improved semiconductor arithmetic unit having add-subtract control and function bypass control.
A more specific object of the invention is to provide a full binary subtracter having means to bypass a subtrahend which would produce a negative difference and also having means to produce a signal representing a borrow which would have been generated if the subtrahend had not been bypassed. Briefly, in accomplishing the foregoing object in a preferred embodiment of the invention, there is provided a full binary adder-subtracter having add, subtract and bypass control terminals.
When the bypass control signal is activated, a function such as an add or subtract operation is bypassed so that the input appears at the output unaffected by the function, but at the same time, there is generated a signal representing the effect a borrow or carry of the function as if it had not been bypassed.
Brief description of the drawings The foregoing and other objects and advantages of the invention will become apparent from the following description read in conjunction with the accompanying drawings in which:. FIGURE 1 is a logic diagram of an improved binary arithmetic unit utilizing suppression logic having add-subtract control and function bypass control;. FIGURE 3b is a schematic block diagram of a portion of a matrix or arithmetic complex in which the improved arithmetic unit is particularly useful; and.
Description of the preferred embodiment In FIG. At the same time, it adds to such a matrix the novel feature of bypass or K control described earlier.
As such, it must be capable of adding one to three bits on command and producing a sum and, if required, a carry signal. Furthermore, in performing division, it must be capable of subtracting one or two bits from zero or one and producing the proper difference and borrow signals. Beyond these requirements, and as described in detail below, it must be capable of producing appropriate carry or borrow signals without affecting the sum or difference signals under certain conditions.
The buffer B of FIG. When an N signal i. Terminals 10 and 11 receive the bit signals of the augend or minuend and addend or subtrahend , respectively, and terminal 19 receives the carry in or borrow in signal from the next lower order stage. The control input terminals 16, 28 and 32 receive control signals which set the mode of the arithmetic unit and will be discussed later.
The sum or difference signal appears on terminal 38 and the carry out or borrow out on terminal Operation of the improved arithmetic unit as a full binary adder will now be described for the eighth condition, or row 8, of Truth Table No.
For this condition, the inputs are:. At the same time, the Y on terminal 11 produces a Y at the inputs of suppressors 14 and Suppressor 14 however is closed by the control input Y supplied by buffer 13 resulting in an N on line On the other hand, the Y on the input of suppressor 15 is transmitted to the output of 15 since the gate is open because of the N signal impressed thereon from the K control entry, The Y on the output of 15 is impressed on one input of OR gate 17 causing a Y in the suppressor Suppressor 31, however is closed because of the Y control gate signal impressed from Shh input The result is an N signal on the output of suppressor 31 being impressed on the input of buffer 34 causing an N signal on the output of 34 and on line Output of 17 and q n ly a Y on the inp of Similarly, the N signal on line 42 and the Y signal suppressor It will be noted also that the Y on input on li 39 are impressed as inputs t OR gat 26, proterm nal 10 is impressed on one input of OR gate 1 ducing aY in the output of OR gate 26 which is impressed causlng a Y in Output of 17 a on the input of suppressor Suppressor 29 is open be- The Y the mput of ,Suppressor 18 not translmtted 10 cause of the N signal received from m input 28; therehowever, since gate 18 is closed due to the action of fore there will be a Y Signal appearing on the Output the Y signal from buffer 13 which is impressed on the of Suppressor 29 and accoidingly on line 46 controlmput of gate It will be recalled that the output of OR gate 26 was It W noted that the Y slgnal m the output a Y signal appearing on line Now considering AND of buffer 1s Impressed 15 gate 30, it is apparent that one input of this gate is sup- The critical signal conditions as of this stage in the plied from input 16 the K control input, which is an explanatlon can be Summarized as follows: I 20 is impressed as an input to OR gate These two f inputs combine to produce a Y signal in the output Lme 39 Y of OR gate 33, which is impressed as an in ut to butter Lme 40 N 35, resulting in a Y signal output from buffer 35 which Lme 41 N 25 appears on line 47 and thence on output terminal 38, Input 19 Y which is the sum or difference output of the add-subtract Resuming the description from this point, it can be seen f yi the slgnal 0n 'llne a d he Y that the Y signal at input 19 and the N signal on line slgnal 4 46, an?
P as Inputs g t are both impressed as inputs to AND gate The Y signal on input 19 is also applied as an input to suppressor Since the control gate of suppressor 22 is driven by the N signal from buffer 21, there will be a Y signal in the output of suppressor 22 which will appear on line In like fashion, the Y signal on input 19 is also impressed as an input to suppressor The control gate of this suppressor has an N signal from the K control input 16;.
The other input to OR gate 24 is the N signal on line However, by the truth table for OR gates, only one Y signal is required to produce a Y signal in the output and, therefore, there will be a Y signal from the output of OR gate 24 applied to the input of suppressor The control gate of suppressor 25 is driven by the N signal from buffer 21, therefore, there will be a Y appearing at the output of suppressor 25 and impressed on line Finally, the N signal output of butter 21 appears on line With the foregoing in mind, let us now review the logic required of an arithmetic unit if it is to fulfill the requirements of such a unit in an arithmetic complex.
FIGURE 3b shows a plurality of similar arithmetic units arranged in a matrix to perform calculations as described in more detail in co-pending application Ser. Let us now consider unit AU from row 1, column 3, of the matrix. K or not add; S or no subtract; and K or bypass. For the operation of add, as reqiured in addition, multiplication, power generation, etc. Y signal indicating do not substract S. No signal, or N, indicating do not add, i.
The logic arguments for this operation may be stated as follows: Y signal, on the T output terminal, and there must not be a carry output, i. Continuing this one step further, by substituting 1s and zeros for the signals or no signals respectively, one can summarize the add operations to the eight possibilities shown in truth table number 1.
For application of the arithmetic unit to the general operation of multiply, wherein the various multiplication partial products are supplied to a matrix multiplier as addends, it is obvious that the add operation pertains throughout all phases.
Divide, on the other hand, is conventionally performed as a series of trial subtractions. In co-pe'nding application, Ser. Reference should be made to that application for greater understanding of the process. It is sufficient here to state, however, that in the case of a not-permitted subtraction in the division or root taking process, it is essential that an unsatisfied borrow signal one that, if it were used, would cause a negative difference be maintained to indicate the unsatisfied, or not-permitted, subtraction condition.
At the same time, in such a case it is required that the inputs appearing at the E and F terminals of the particular row of the matrix of arithmetic units not affect the output signals appearing at the T terminals. In other words, the information at the P terminals of the row must be repeated at the T terminals of that row, and the borrow conditions if the E and F inputs of that row are used must be maintained.
For this reason, there is provided as an important feature of this invention, a bypass or K control circuit. The need for K or bypass control in add operations is not as obvious, but there are certain conditions in the evaluation of mathematical series or in curve fitting where it is desirable to have this bypass capability.
For example, it is advantageous to know when the addition of a certain sum causes a carry to be extended to the left beyond a certain column of the matrix. If there are undue mathematical calculations or test operations, then this particular certain sum should be recorded continually in the add matrix, yet its effect on the total be nil.
A description of the function of the K control requires reference again to FIG. In the case of subtraction, the. Looking at FIGURE 1, it is seen that the application of a K control signal to terminal 16 by means of suppressor gates and 23 prevents any input signal supplied to subtrahend input 11 or to borrow input 19, respectively, from entering the sum chains formed by elements 17, 18, 40, 24, 25, 43, 33, 35, 47, and T or sum output terminal Adders Adders are the basic building blocks of all arithmetic circuits; adders add two binary numbers and give out sum and carry as output.
Basically we have two types of adders. This operation is called half addition and the circuit to realize it is called a half adder. Full Adder Full adder takes a three-bits input.
Adding two single-bit binary values X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit. The basis of the circuit below is from the above Kmap. Each full adder represents a bit position j from 0 to n The output of a full adder at position j is given by: Cj In the expression of the sum Cj must be generated by the full adder at lower position j. Carry Look-Ahead Adder The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that are added because the carry signals have to propagate from one full-adder to the next.
For large values of N, the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate the calculation of the carry bits. This solution involves a "look-ahead carry generator" which is a block that simultaneously calculates all the carry bits involved. The design of the look-ahead carry generator involves two Boolean functions named Generate and Propagate. For each input bits pair these functions are defined as: In the first case, the carry bit is activated by the local conditions the values of Xi and Yi.