Modified duobinary signaling mirror
The embodiment is described as follows. The precoder in the transmitter 51 includes an AND gate as a first logic circuit and a divided-by-two circuit and is obviously dissimilar to the conventional precoder.
Based on the above-mentioned, as shown in FIG. As shown, the receiver 53 includes a decoder and an adaptive reference voltage control loop , wherein the decoder includes a comparator and a second logic circuit The detailed descriptions of the comparator in the decoder are illustrated in the FIG.
In the meanwhile, the comparator compares a voltage value V 1 at a drain D of the positive terminal of the second NMOS M 2 of the first differential amplifier with a voltage value V 2 at a drain D of the negative terminal of the third NMOS M 3 of the second differential amplifier to generate a first comparison result a bit, the first comparison result means a least significant bit, LSB and the comparator compares a voltage value V 3 at a drain D of the positive terminal of the first NMOS M 1 of the first differential amplifier with a voltage value V 3 at a drain D of the positive terminal of the forth NMOS M 4 of the second differential amplifier to generate a second comparison result a bit, the second comparison result is a most significant bit, MSB.
And then the comparator regards the first and the second differential amplifiers with different bias current as a comparator having a first reference voltage and a comparator having a second reference voltage based on the described circuit, wherein the first and the second reference voltages are different.
Hitherto, the differential signal y 3 from the XOR gate is transmitted into other logic circuits for signal processing. However, the differential signal y 3 from the XOR gate is simultaneously transmitted to the adaptive reference voltage control loop in the receiver 53 to dynamically adjust the two different bias currents of the differential amplifiers and Still further, and as explained in FIG. In the adaptive reference voltage control loop , the filter filters the voltage of the differential signal y 3 from the XOR gate Referring now to FIG.
According to the allocated steady current I 1 , the mirrors and convert and output a first and a second control current signals CI 1 and CI 2 , respectively. That is, the first control current signal CI 1 from the first current mirror and the second control current signal CI 2 from the second current mirror can change the first reference voltage of the comparator and the second reference voltage of the comparator Finally, noise generated from the channel can cause the distortion of the digital signals, which should be avoided.
However, the conventional receiver using two comparators with reference voltages, which are manually set or predetermined based on the voltage of the three-level binary signal.
The first and the second current mirrors proposed by the invention dynamically adjust the first and the second differential amplifiers with two different bias current, respectively-that means the first control current generated by the first current mirror and the second control current generated by the second current mirror can change the two reference voltages of the comparator with the first reference voltage and the second reference voltage.
In other words, the comparator in the receiver is not manually operated. Furthermore, as the concept of IC design, the transceiver proposed the invention have cost effective advantages that it requires only one comparator when compared to the conventional transceiver including two comparators.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Year of fee payment: The present invention relates to a duobinary transceiver. Specifically, the duobinary transceiver circuit proposed by the invention provides a new circuit configure of a precoder in a typical transceiver and a decoder in a typical receiver, based on a conventional transceiver including a transmitter, a transmission medium, and a receiver. SUMMARY OF THE INVENTION In view of above, an embodiment of the present invention provides an duobinary transceiver with a high data transmission rate that is free from the drawbacks described above, and the another circuits proposed by the invention are implemented in a conventional precoder and in a conventional receiver respectively based on the conventional transceiver, which includes a transmitter, a transmission medium and a receiver.
According to an aspect of the present invention, there is provided a duobinary transceiver circuit, comprising: What is claimed is: A duobinary transceiver, comprising: A duobinary transceiver of claim 1 , wherein the first digital signal includes a non-return-to-zero signal and the transmitter has a precoder including the first logic circuit and the divided-by-two circuit. A duobinary transceiver of claim 2 , wherein the transmitter further comprises an equalizer coupled to the precoder, and compensating the coded digital signal.
A duobinary transceiver of claim 1 , wherein the transmission medium is selected from one of a copper cable, optical fiber and a printed circuit board. A duobinary transceiver of claim 1 , wherein the receiver further comprises a decoder including the comparator and the second logic circuit, wherein the comparator has a comparison reference voltage and compares the duobinary digital signal with the comparison reference voltage to generate a two-bit comparison result.
A duobinary transceiver of claim 5 , wherein the comparator comprises: A duobinary transceiver of claim 7 , wherein the first differential amplifier has a first reference voltage, the second differential amplifier has a second reference voltage, and the comparison reference voltage is one of the first and the second reference voltages.
A duobinary transceiver of claim 7 , wherein the comparator compares a voltage at the positive terminal of the first differential amplifier with a voltage at the negative terminal of the second differential amplifier to generate a first comparison result, and compares a voltage at the negative terminal of the first differential amplifier with a voltage at the positive terminal of the second differential amplifier to generate a second comparison result.
A duobinary transceiver of claim 9 , wherein each of the first and the second comparison results is a one-bit result. A duobinary transceiver of claim 5 , wherein the receiver further comprises two hysteresis buffers for amplifying the two-bit comparison results from the comparator.
A receiver of claim 12 , wherein the comparator comprises: A receiver of claim 14 , wherein the first differential amplifier has a first reference voltage, the second differential amplifier has a second reference voltage, and the comparison reference voltage is one of the first and the second reference voltages. A receiver of claim 14 , wherein the comparator compares a voltage at the positive terminal of the first differential amplifier with a voltage at the negative terminal of the second differential amplifier to generate a first comparison result and compares a voltage at the negative terminal of the first differential amplifier with a voltage at the positive terminal of the second differential amplifier to generate a second comparison result.
A receiver of claim 16 , wherein each of the first and the second comparison results is a one-bit result. A receiver of claim 12 , wherein the receiver further comprises two hysteresis buffers for amplifying the two-bit comparison results from the comparator. Digital filter, partial response equalizer, and digital coherent receiver device and method.
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While conventional binary transmission techniques may be, and have been, used in low-speed applications, multi-level systems, including the duobinary, modified duobinary, quaternary and higher level systems, are finding increasing use because of their high-speed capabilities. The modified duobinary data transmission system is described in U. In the transmission of information by digital signals, a series of time-divided equal intervals, called time slots, are employed.
In such digital transmission systems, the applied signals are discrete in both time and amplitude, with the time duration of each signal element confined to one time slot. To recover the transmitted information, the received signal must be sampled in each time slot so as to determine the character of the signal element in each time slot. Because of degradation which occurs during transmission, the received signal is normally equalized to compensate for the most serious transmission path distortions of the signal and is amplified to attain an amplitude more nearly like that of the original signal.
What is then required is a clock timing signal which permits sampling of each time slot at or near the optimum sampling time so that the discrete amplitudes originally transmitted may be reconstituted. For binary, bipolar and the baseband duobinary signals, as well as for other digital signals of this type, acceptable timing signals may be obtained from the equalized and amplified received signal by nonlinear processing rectification and clipping , which introduces a discrete component at the signaling rate.
This is followed by a frequency selection circuit which may be a high Q narrow-band bandpass filter tuned to the timing frequency to extract the desired sinusoidal timing component of the input signal. This sinusoidal timing component is then amplified and limited to produce an approximate square wave at the signaling rate. Generally, the output is then applied to a pulse generator which generates narrow sampling pulses at a particular edge of the square wave.
Phase shift correction is often necessary, and a phase shifter may be employed in the timing path to adjust the phase of the timing pulse so that the sample pulses occur at the proper location in each time slot. A brief discussion of timing recovery is included at pages - of the text "Transmission Systems For Communications", revised fourth edition, December , Bell Telephone Laboratories, Inc. A technique for producing a timing signal from a modified duobinary digital signal is disclosed in U.
It was noted therein the simple rectification technique disclosed hereinabove did not work well for the modified duobinary signals because of the intersymbol interference and phase structure, which caused the resultant timing signal to vanish. To overcome this problem, the technique disclosed employed a plurality of full-wave rectifiers.
This was necessary to obtain a discrete component at the timing frequency from the modified duobinary signal prior to filtering. A circuit arrangement is disclosed in which the recovery of the timing information from an equalized pseudo-ternary waveform is obtained by means of the combination of amplifying, peak-amplitude detecting and slicing circuits which are provided by integrated circuits and in which the functions of a-c coupling, peak amplitude storing and phase correcting are provided by discrete components.
Referring now to FIG. The equalized and amplified pseudo-ternary signal is applied via path 2 to buffer amplifier 4. The output of amplifier 4 is a-c coupled along path 6 through capacitor 8 to a precision differential amplifier Amplifier 12 includes a precision gain amplifier which provides both inverted and noninverted outputs in response to the positive and negative excursions, respectively, of the pseudo-ternary signal.
These separate outputs appear on paths 14 and 18 where they are directly applied to peak detector 22 and, via connections to paths 16 and 20, to slicer and summer The peak output voltage, V c , from peak detector 22 is stored in discrete capacitor 27, and this peak voltage is applied via path 24 to the input of slicer and summer The peak voltage V c is used as a reference in establishing a slicing reference voltage level V s.
Discrete capacitor 28 is used to provide a low impedance circuit to ground, thus bypassing transients and minimizing variations in the slicer reference voltage V s. The upper portions of the pulses from amplifier 12 are selected by the slicer and summed together to obtain a series of positive-going pulses in a synchronism with the input signal pulses and are applied to amplifier 32 via path 30 and thence to a clock retiming circuit, not shown, via path A current source 36 provides the reference current to buffer 4, precision amplifier 12, slicer and summer 26, and amplifier Resistors R16 and R17 and transistor Q13 form the basic current reference source for the integrated circuit.
As is well known, a low supply voltage is required for implementation of a circuit into bipolar IC technology.
The current in all other current sources is in the ratio of R17 to the emitter resistor of the other sources times the current in R Transistor Q2 is an active load for transistor Q1. Transistor Q1 is a unity voltage gain amplifier buffer amplifier used to prevent loading of the input signal, and its output is a-c coupled via discrete capacitor C1 to the base of transistor Q6 via resistor R9.
Transistors Q3 through Q10 and associated elements form a self-biased precision gain amplifier which provides both inverted and noninverted outputs from the collectors of Q6 and Q7, which are referenced to 0. This potential is independent of the magnitude of the power supply sources.
The availability of both the inverted and noninverted outputs is desirable because, as noted hereinabove, the input pseudo-ternary signal to the device consists of both positive and negative signal pulses. A first bias source is obtained from a current source consisting of transistor Q10 drawing current through resistor R This sets the bias voltage at the base of transistor Q9. The bias at the emitter of transistor Q9 is then equal to the base bias voltage of Q9 minus the base-emitter voltage of 0.
Resistor R13 is a passive load for transistor Q9. The input signal to this gain stage is a-c coupled to the base of transistor Q6 via capacitor 6. Resistors R9 and R10 form a voltage divider that attenuates the input signal. Resistor R11 compensates for any offsets that would occur due to the base current of transistor Q6 flowing through resistor R A second bias source is controlled by transistor Q8 which provides a current source for the differential amplifiers Q6 - Q7.
A third bias source provides a d-c reference for the collectors of the differential pair consisting of transistors Q6 and Q7. This third bias source is controlled by transistor Q4 via transistor Q5. What is desired here is to keep the bias point of the collectors of transistors Q6 and Q7 at 0.
Matched resistors R5 and R6 are the Q6 and Q7 collector voltage sense resistors. This induces more current to flow through resistor R2, lowering the voltage at the base of transistor Q5 which, in turn, lowers the supply voltage to the matched load resistors, R3 and R4, of the differential pair transistors Q6 and Q7.
Since the current is fixed through resistors R3 and R4, so is the voltage drop across each resistor. Therefore, as the voltage at the top of resistors R3 and R4 is lowered, the collector voltage of transistors Q6 and Q7 also drops. Thus, the loop maintains an exact bias voltage of one base-emitter above ground for the collectors of transistors Q6 and Q7.
Transistor Q3 is connected as a capacitor to prevent oscillations in the feedback loop. The equivalent collector resistance of the Q6 side of the differential pair, consisting of transistors Q6 and Q7, is resistor R4 in parallel with resistor R5.
Thus, the overall gain from the input is EQU1. The peak detector is comprised of transistors Q11 and Q The function of the peak detector is to find the peak height of the incoming waveform for both the positive and negative excursions. The base of transistor Q11 has one phase of the incoming signal at its base input while the base of Q12 receives the opposite phase.
A peak holding capacitor 27 has one end connected to the emitters of transistors Q11 and Q12 and to the base of Q The other end of capacitor 27 is connected to the common reference When the signal at the collector of transistor Q7 reaches its peak value, transistor Q12 is turned on and charges the capacitor to the maximum amplitude of the waveform.